1. Field of the Invention
The present invention relates to a formation method for a metal element, a production method for a semiconductor device, a production method for an electronic device, a semiconductor device and an electronic device, as well as an electronic equipment.
Priority is claimed to Japanese Patent Application No. 2003-7047, filed Jan. 15, 2003, which is incorporated herein by reference.
2. Description of Related Art
Conventionally, the metal elements used within semiconductor devices and electronic devices have frequently used metals such as Al (aluminum). However, as the demands increase for ever smaller and faster semiconductor devices, and higher performance electronic devices, it is becoming increasingly difficult to ensure an adequate level of performance with aluminum wiring or the like. Copper wiring techniques, which offer superior electromigration resistance to aluminum and also provide low resistance, are attracting considerable attention as one potential solution to this problem, and are being widely investigated for potential applications.
In the formation of a metal element from copper, the properties of copper mean that etching methods are not particularly suitable, and consequently, a process known as damascene is used, in which copper metal is used to fill preformed grooves. In such a damascene process, predetermined grooves are formed in advance in the treatment surface of an interlayer insulating film formed from silicon oxide or the like, copper metal is subsequently used to fill those grooves, and then any excess copper metal is removed by CMP (Chemical Mechanical Polishing).
An example of a known method that can be used for forming a film of copper metal within these grooves is a method in which a seed layer is first formed, and then a plating layer is formed from this seed layer, as is shown, for example, in Japanese Patent Application Laid-Open (JP-A) No. Heisei 11-238703. The seed layer is formed using a sputtering method or the like, and is formed across the entire surface of the interlayer insulating film, including the grooves. Furthermore, the plating layer is formed by depositing metal atoms within a plating liquid onto the seed layer.
However, in the technique disclosed above, during the formation of the seed layer, the sputtering method forms the seed layer across the entire surface of the interlayer insulating film, and it is not possible to form the seed layer only within certain desired positions.
Furthermore, because the seed layer is formed across the entire treatment surface, the plating layer also gets formed across the entire surface, meaning the excess copper metal must then be removed by a CMP method, which is essentially a wasted method.
In addition, in order to remove all of the excess copper metal during the CMP method, at least the surface of the interlayer insulating film must also be polished, and consequently, a comparatively hard material such as SiO2 or the like must be used for the interlayer insulating film. This results in an undesirable restriction in the number of materials that can be selected for use as the interlayer insulating film.
Furthermore, when a damascene process is used to form multilayer interlayer insulating films, that is, during formation of a so-called dual damascene structure, an etching stop layer must be formed between respective interlayer insulating films, which results in an undesirable increase in the number of steps in the method.
The present invention takes the above circumstances into consideration, with an object of providing a metal element formation method for forming a metal element from a selected material such as copper metal, which does not require the use of CMP, as well as providing a production method for a semiconductor device, a production method for an electronic device, a semiconductor device and an electronic device, and an electronic equipment.